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| (R) STD12N10L N - CHANNEL 100V - 0.12 - 12A TO-252 LOW THRESHOLD POWER MOS TRANSISTOR TYPE STD12N10L s s s s s s s V DSS 100 V R DS(o n) < 0.15 ID 12 A TYPICAL RDS(on) = 0.12 AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED HIGH CURRENT CAPABILITY 175 oC OPERATING TEMPERATURE LOW THRESHOLD DRIVE FOR THROUGH-HOLE VERSION CONTACT SALES OFFICE 3 1 DPAK TO-252 (Suffix "T4") APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SOLENOID AND RELAY DRIVERS s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC & DC-AC CONVERTERS s AUTOMOTIVE ENVIRONMENT(INJECTION, ABS, AIR-BG, LAMPDRIVERS, Etc.) INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR VGS ID ID I DM (*) P tot T st g Tj Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 k) Gate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) Total Dissipation at T c = 25 C Derating F actor Storage T emperature Max. Operating Junction Temperature o o o Value 100 100 15 12 8 48 50 0.33 -65 to 175 175 Unit V V V A A A W W /o C o o C C (*) Pulse width limited by safe operating area November 1999 1/9 STD12N10L THERMAL DATA R thj -case R thj -amb R thc-sink Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Case-sink Maximum Lead Temperature F or Soldering Purpose Max Max T yp 3 100 1.5 275 o o C/W C/W o C/W o C ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 A V GS = 0 Min. 100 1 10 100 Typ. Max. Unit V A A nA V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = 15 V T c = 125 oC ON () Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10V V GS = 5V Test Con ditions ID = 250 A ID = 6 A ID = 6 A 12 Min. 1 Typ. 1.6 0.12 0.17 Max. 2.5 0.15 0.2 Unit V A V DS > ID(o n) x R DS(on )ma x V GS = 10 V DYNAMIC Symbo l g f s () C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz ID = 6 A V GS = 0 Min. 6.5 Typ. 10 800 150 50 Max. Unit S pF pF pF 2/9 STD12N10L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay T ime Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 50 V ID = 6 A R G = 4.7 V GS = 5 V (Resistive Load, see fig. 3) V DD = 80 V ID = 12 A V GS = 5 V Min. Typ. 15 40 20 6 10 30 Max. Unit ns ns nC nC nC SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions V DD = 80 V I D = 12 A V GS = 5 V R G = 4.7 (Induct ive Load, see fig. 5) Min. Typ. 12 12 25 Max. Unit ns ns ns SOURCE DRAIN DIODE Symbo l ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 12 A V GS = 0 145 580 8 I SD = 12 A di/dt = 100 A/s o T j = 150 C V DD = 30 V (see test circuit, fig. 5) Test Con ditions Min. Typ. Max. 12 48 1.5 Unit A A V ns C A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area 3/9 STD12N10L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/9 STD12N10L TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397 DIM. H A C2 C DETAIL "A" A1 L2 D DETAIL "A" B = = 3 B2 = = G E 2 L4 1 = = A2 0068772-B 5/9 STD12N10L Information furnished is believed to be accurate and reliable. However, STMicroelect onics assumes no responsibil ity for the consequences r of use of such information nor for any infringement of patents or other rights of third partes which may result from its use. No license is i granted by implication or otherwise under any patent or patent rights of STMicroelectro nics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all informaton previously supplied. STMicroelectronics products i are not authorized for use as critical components in life support devices or systems with express written approval of STMicroelectronics. out The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa - Malaysia - Malta - Morocco n Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 6/9 http://www.st.com . |
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